Specification Sheet
Datasheet, Volume 2 of 2 379
PCI Express* Controller (x16) Registers
12.26 Power Management Control/Status (PM)—Offset
84h
Access Method
Default: 8h
21
0h
RO
DSI: Device Specific Initialization: Hardwired to 0 to indicate that special initialization
of this device is NOT required before generic class device driver is to use it.
20
0h
RO
APS: Auxiliary Power Source: Hardwired to 0.
19
0h
RO
PMECLK: PME Clock: Hardwired to 0 to indicate this device does NOT support PMEB
generation.
18:16
3h
RO
PCIPMCV: PCI PM CAP Version: Version - A value of 011b indicates that this function
complies with revision 1.2 of the PCI Power Management Interface Specification.
--Was Previously Hardwired to 02h to indicate there are 4 bytes of power management
registers implemented and that this device complies with revision 1.1 of the PCI Power
Management Interface Specification.
15:8
90h
RO_V
PNC: Pointer to Next Capability: This contains a pointer to the next item in the
capabilities list. If MSICH (CAPL[0] @ 7Fh) is 0, then the next item in the capabilities
list is the Message Signaled Interrupts (MSI) capability at 90h. If MSICH (CAPL[0] @
7Fh) is 1, then the next item in the capabilities list is the PCI Express capability at A0h.
7:0
1h
RO
CID: Capability ID: Value of 01h identifies this linked list item (capability structure) as
being for PCI Power Management registers.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:1, F:0] + 84h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
RSVD
PMESTS
DSCALE
DSEL
PMEE
RSVD
NSR
RSVD
PS
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0h
RO
Reserved (RSVD): Reserved.
15
0h
RO
PMESTS: PME Status: Indicates that this device does not support PMEB generation
from D3cold.
14:13
0h
RO
DSCALE: Data Scale: Indicates that this device does not support the power
management data register.
12:9
0h
RO
DSEL: Data Select: Indicates that this device does not support the power
management data register.