Specification Sheet
PCI Express* Controller (x16) Registers
378 Datasheet, Volume 2 of 2
12.25 Power Management Capabilities (PM)—Offset 80h
Access Method
Default: C8039001h
2
0h
RW
ISAEN: ISA Enable: Needed to exclude legacy resource decode to route ISA resources
to legacy decode path. Modifies the response by the root port to an I/O access issued
by the Processor that target ISA I/O addresses. This applies only to I/O addresses that
are enabled by the IOBASE and IOLIMIT registers.
0: All addresses defined by the IOBASE and IOLIMIT for Processor I/O transactions
will be mapped to PCI Express-G.
1: The root port will not forward to PCI Express-G any I/O transactions addressing the
last 768 bytes in each 1KB block even if the addresses are within the range defined by
the IOBASE and IOLIMIT registers.
1
0h
RW
SERREN: SERR Enable:
0: No forwarding of error messages from secondary side to primary side that could
result in an SERR.
1: ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in SERR message
when individually enabled by the Root Control register.
0
0h
RW
PEREN: Parity Error Response Enable: Controls whether or not the Master Data Parity
Error bit in the Secondary Status register is set when the root port receives across the
link (upstream) a Read Data Completion Poisoned TLP
0: Master Data Parity Error bit in Secondary Status register can NOT be set.
1: Master Data Parity Error bit in Secondary Status register CAN be set.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:1, F:0] + 80h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
PMES
D2PSS
D1PSS
AUXC
DSI
APS
PMECLK
PCIPMCV
PNC
CID
Bit
Range
Default &
Access
Field Name (ID): Description
31:27
19h
RO
PMES: PME Support: This field indicates the power states in which this device may
indicate PME wake via PCI Express messaging. D0, D3hot & D3cold. This device is not
required to do anything to support D3hot & D3cold, it simply should report that those
states are supported. Refer to the PCI Power Management 1.1 specification for
encoding explanation and other power management details.
26
0h
RO
D2PSS: D2 Power State Support: Hardwired to 0 to indicate that the D2 power
management state is NOT supported.
25
0h
RO
D1PSS: D1 Power State Support: Hardwired to 0 to indicate that the D1 power
management state is NOT supported.
24:22
0h
RO
AUXC: Auxiliary Current: Hardwired to 0 to indicate that there are no 3.3Vaux
auxiliary current requirements.