Specification Sheet

Datasheet, Volume 2 of 2 45
Processor Configuration Register Definitions and Address Ranges
2.9.1 IOBAR Mapped Access to Device 2 MMIO Space
Device 2, Processor Graphics, contains an IOBAR register. If Device 2 is enabled,
Processor Graphics registers or the GTT table can be accessed using this IOBAR. The
IOBAR is composed of an index register and a data register.
MMIO_Index: MMIO_INDEX is a 32-bit register. A 32-bit (all bytes enabled) I/O write
to this port loads the offset of the MMIO register or offset into the GTT that needs to be
accessed. An I/O Read returns the current value of this register. I/O read/write
accesses less than 32 bits in size (all bytes enabled) will not target this register.
MMIO_Data: MMIO_DATA is a 32-bit register. A 32-bit (all bytes enabled) I/O write to
this port is re-directed to the MMIO register pointed to by the MMIO-index register. An
I/O read to this port is re-directed to the MMIO register pointed to by the MMIO-index
register. I/O read/write accesses less than 32 bits in size (all bytes enabled) will not
target this register.
The result of accesses through IOBAR can be:
• Accesses directed to the GTT table. (that is, route to DRAM)
• Accesses to Processor Graphics registers with the device.
• Accesses to Processor Graphics display registers now located within the PCH. (that
is, route to DMI).
Note: GTT table space writes (GTTADR) are supported through this mapping mechanism.
This mechanism to access Processor Graphics MMIO registers should NOT be used to
access VGA I/O registers that are mapped through the MMIO space. VGA registers
should be accessed directly through the dedicated VGA I/O ports.
2.9.2 Trusted Graphics Ranges
Trusted graphics ranges are NOT supported.
2.10 System Management Mode (SMM)
The Core handles all SMM mode transaction routing. The platform does not support
HSEG, and the processor will does not allow I/O devices access to CSEG/TSEG/HSEG
ranges.
DMI Interface and PCI Express* masters are Not allowed to access the SMM
space.
Table 2-4. SMM Regions
SMM Space Enabled Transaction Address Space DRAM Space (DRAM)
Compatible (C) 000A_0000h to 000B_FFFFh 000A_0000h to 000B_FFFFh
TSEG (T) (TOLUD – STOLEN – TSEG) to
TOLUD – STOLEN
(TOLUD – STOLEN – TSEG) to TOLUD –
STOLEN