Specification Sheet

Datasheet, Volume 2 of 2 375
PCI Express* Controller (x16) Registers
12.21 Capabilities Pointer (CAPPTR)—Offset 34h
The capabilities pointer provides the address offset to the location of the first entry in
this device's linked list of capabilities.
Access Method
Default: 88h
12.22 Interrupt Line (INTRLINE)—Offset 3Ch
This register contains interrupt line routing information. The device itself does not use
this value, rather it is used by device drivers and operating systems to determine
priority and vector information.
Access Method
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PMLIMITU
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0h
RW
PMLIMITU: Prefetchable Memory Address Limit: Corresponds to A[63:32] of the
upper limit of the prefetchable Memory range that will be passed to PCI Express-G.
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:1, F:0] + 34h
7 4 0
1 0 0 0 1 0 0 0
CAPPTR1
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
88h
RO
CAPPTR1: First Capability: The first capability in the list is the Subsystem ID and
Subsystem Vendor ID Capability.
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:1, F:0] + 3Ch