Specification Sheet
PCI Express* Controller (x16) Registers
372 Datasheet, Volume 2 of 2
12.17 Prefetchable Memory Base Address (PMBASE)—
Offset 24h
This register in conjunction with the corresponding Upper Base Address register
controls the Processor to PCI Express-G prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE =< address =< PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Base Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
should be initialized by the configuration software. For the purpose of address decode
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory
address range will be aligned to a 1MB boundary.
Access Method
Default: FFF1h
12.18 Prefetchable Memory Limit Address (PMLIMIT)—
Offset 26h
This register in conjunction with the corresponding Upper Limit Address register
controls the Processor to PCI Express-G prefetchable memory access routing based on
the following formula:
PREFETCHABLE_MEMORY_BASE =< address =< PREFETCHABLE_MEMORY_LIMIT
The upper 12 bits of this register are read/write and correspond to address bits
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Limit Address register are
read/write and correspond to address bits A[39:32] of the 40-bit address. This register
should be initialized by the configuration software. For the purpose of address decode
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory
address range will be at the top of a 1MB aligned memory block. Note that prefetchable
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:0] + 24h
15 12 8 4 0
1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1
PMBASE
AS64
Bit
Range
Default &
Access
Field Name (ID): Description
15:4
FFFh
RW
PMBASE: Prefetchable Memory Base Address: Corresponds to A[31:20] of the lower
limit of the memory range that will be passed to PCI Express-G.
3:0
1h
RO
AS64: 64-bit Address Support: Indicates that the upper 32 bits of the prefetchable
memory region base address are contained in the Prefetchable Memory base Upper
Address register at 28h.