Specification Sheet

Datasheet, Volume 2 of 2 371
PCI Express* Controller (x16) Registers
12.16 Memory Limit Address (MLIMIT)—Offset 22h
This register controls the Processor to PCI Express-G non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE=< address =<MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-
only and return zeros when read. This register should be initialized by the configuration
software. For the purpose of address decode address bits A[19:0] are assumed to be
FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1MB
aligned memory block.
Note: Memory range covered by MBASE and MLIMIT registers are used to map non-
prefetchable PCI Express-G address ranges (typically where control/status memory-
mapped I/O data structures of the graphics controller will reside) and PMBASE and
PMLIMIT are used to map prefetchable address ranges (typically graphics local
memory). This segregation allows application of USWC space attribute to be performed
in a true plug-and-play manner to the prefetchable address range for improved CPU-
PCI Express memory access performance.
Note also that configuration software is responsible for programming all address range
registers (prefetchable, non-prefetchable) with the values that provide exclusive
address ranges i.e. prevent overlap with each other and/or with the ranges covered
with the main memory. There is no provision in the Processor hardware to enforce
prevention of overlap and operations of the system in the case of overlap are not
guaranteed.
Access Method
Default: 0h
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:0] + 22h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MLIMIT
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
15:4
0h
RW
MLIMIT: Memory Address Limit: Corresponds to A[31:20] of the upper limit of the
address range passed to PCI Express-G.
3:0
0h
RO
Reserved (RSVD): Reserved.