Specification Sheet

PCI Express* Controller (x16) Registers
370 Datasheet, Volume 2 of 2
12.15 Memory Base Address (MBASE)—Offset 20h
This register controls the Processor to PCI Express-G non-prefetchable memory access
routing based on the following formula:
MEMORY_BASE=< address =<MEMORY_LIMIT
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32 bit address. The bottom 4 bits of this register are read-
only and return zeros when read. This register should be initialized by the configuration
software. For the purpose of address decode address bits A[19:0] are assumed to be 0.
Thus, the bottom of the defined memory address range will be aligned to a 1MB
boundary.
Access Method
Default: FFF0h
10:9
0h
RO
DEVT: DEVSELB Timing: Not Applicable or Implemented. Hardwired to 0.
8
0h
RW1C
SMDPE: Master Data Parity Error: When set indicates that the Processor received
across the link (upstream) a Read Data Completion Poisoned TLP (EP=1). This bit can
only be set when the Parity Error Enable bit in the Bridge Control register is set.
7
0h
RO
FB2B: Fast Back-to-Back: Not Applicable or Implemented. Hardwired to 0.
6
0h
RO
Reserved (RSVD): Reserved.
5
0h
RO
CAP66: 66/60 MHz capability: Not Applicable or Implemented. Hardwired to 0.
4:0
0h
RO
Reserved (RSVD): Reserved.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:0] + 20h
15 12 8 4 0
1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0
MBASE
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
15:4
FFFh
RW
MBASE: Memory Address Base: Corresponds to A[31:20] of the lower limit of the
memory range that will be passed to PCI Express-G.
3:0
0h
RO
Reserved (RSVD): Reserved.