Specification Sheet

Processor Configuration Register Definitions and Address Ranges

44 Datasheet, Volume 2 of 2

2.7.7 Memory Remapping

An incoming address (referred to as a logical address) is checked to see if it falls in the

memory re-map window. The bottom of the re-map window is defined by the value in

the REMAPBASE register. The top of the re-map window is defined by the value in the

REMAPLIMIT register. An address that falls within this window is re-mapped to the

physical memory starting at the address defined by the TOLUD register. The TOLUD

2.7.8 Hardware Remap Algorithm

The following pseudo-code defines the algorithm used to calculate the DRAM address to

be used for a logical address above the top of physical memory made available using

re-claiming.

IF (ADDRESS_IN[38:20] >= REMAP_BASE[35:20]) AND

(ADDRESS_IN[38:20] <= REMAP_LIMIT[35:20]) THEN

ADDRESS_OUT[38:20] = (ADDRESS_IN[38:20] - REMAP_BASE[35:20]) +

0000000b & TOLUD[31:20]

ADDRESS_OUT[19:0] = ADDRESS_IN[19:0]

2.8 PCI Express* Configuration Address Space

PCIEXBAR is located in Device 0 configuration space. The processor detects memory

accesses targeting PCIEXBAR. BIOS should assign this address range such that it will

not conflict with any other address ranges.

2.9 Graphics Memory Address Ranges

Note: Processor Graphics does not apply to X-Series processor.

The integrated memory controller can be programmed to direct memory accesses to

the Processor Graphics when addresses are within any of the ranges specified using

registers in MCH Device 2 configuration space.

• The Graphics Memory Aperture Base Register (GMADR) is used to access graphics

memory allocated using the graphics translation table.

• The Graphics Translation Table Base Register (GTTADR) is used to access the

translation table and graphics control registers. This is part of the GTTMMADR

These ranges can reside above the Top-of-Low-DRAM and below High BIOS and APIC

address ranges. They should reside above the top of memory (TOLUD) and below 4 GB

so they do not take any physical DRAM memory space.

Alternatively, these ranges can reside above 4 GB, similar to other BARs that are larger

than 32 bits in size.

GMADR is a Prefetchable range in order to apply USWC attribute (from the processor

point of view) to that range. The USWC attribute is used by the processor for write

combining.