Specification Sheet

Datasheet, Volume 2 of 2 363
PCI Express* Controller (x16) Registers
Bit
Range
Default &
Access
Field Name (ID): Description
15
0h
RW1C
DPE: Detected Parity Error: This bit is Set by a Function whenever it receives a
Poisoned
TLP, regardless of the state the Parity Error Response bit in the Command register. On
a Function with a Type 1 Configuration header, the bit is Set when the Poisoned TLP is
received by its Primary Side.
Default value of this bit is 0b.
This bit will be set only for completions of requests encountering ECC error in DRAM.
Poisoned Peer 2 peer posted forwarded will not set this bit. They are reported at the
receiving port.
14
0h
RW1C
SSE: Signaled System Error: This bit is set when this Device sends an SERR due to
detecting an ERR_FATAL or ERR_NONFATAL condition and the SERR Enable bit in the
Command register is '1'. Both received (if enabled by BCTRL1[1]) and internally
detected error messages do not affect this field.
13
0h
RO
RMAS: Received Master Abort Status: This bit is Set when a Requester receives a
Completion with
Unsupported Request Completion Status. On a Function with a Type 1 Configuration
header, the bit is Set when the Unsupported Request is received by its Primary Side.
Not applicable. We do not have UR on primary interface
12
0h
RO
RTAS: Received Target Abort Status: This bit is Set when a Requester receives a
Completion with Completer Abort Completion Status. On a Function with a Type
1 Configuration header, the bit is Set when the Completer Abort is received by its
Primary Side.
Default value of this bit is 0b.
Not Applicable or Implemented. Hardwired to 0. The concept of a Completer abort
does not exist on primary side of this device.
11
0h
RO
STAS: Signaled Target Abort Status: This bit is Set when a Function completes a
Posted or Non- Posted Request as a Completer Abort error. This applies to a Function
with a Type 1 Configuration header when the Completer Abort was generated by its
Primary Side.
Default value of this bit is 0b.
Not Applicable or Implemented. Hardwired to 0. The concept of a target abort does not
exist on primary side of this device.
10:9
0h
RO
DEVT: DEVSELB Timing: This device is not the subtractively decoded device on bus 0.
This bit field is therefore hardwired to 00 to indicate that the device uses the fastest
possible decode.
Does not apply to PCI Express and should be hardwired to 00b.
8
0h
RW1C
PMDPE: Master Data Parity Error: This bit is Set by a Requester (Primary Side for
Type 1 Configuration Space header Function) if the Parity Error Response bit in the
Command register is 1b and either of the following two conditions occur
• Requester receives a Completion marked poisoned
• Requester poisons a write Request
If the Parity Error Response bit is 0b, this bit is never Set.
Default value of this bit is 0b.
This bit will be set only for completions of requests encountering ECC error in DRAM.
Poisoned Peer 2 peer posted forwarded will not set this bit. They are reported at the
receiving port.
7
0h
RO
FB2B: Fast Back-to-Back: Not Applicable or Implemented. Hardwired to 0.
6
0h
RO
Reserved (RSVD): Reserved.
5
0h
RO
CAP66: 66/60 MHz capability: Not Applicable or Implemented. Hardwired to 0.