Specification Sheet

Datasheet, Volume 2 of 2 361
PCI Express* Controller (x16) Registers
12.3 PCI Command (PCICMD)—Offset 4h
Access Method
Default: 0h
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:1, F:0] + 4h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
INTAAD
FB2B
SERRE
RSVD
PERRE
VGAPS
MWIE
SCE
BME
MAE
IOAE
Bit
Range
Default &
Access
Field Name (ID): Description
15:11
0h
RO
Reserved (RSVD): Reserved.
10
0h
RW
INTAAD: INTA Assertion Disable:
0: This device is permitted to generate INTA interrupt messages.
1: This device is prevented from generating interrupt messages. Any INTA emulation
interrupts already asserted should be de-asserted when this bit is set.
Only affects interrupts generated by the device (PCI INTA from a PME or Hot Plug
event) controlled by this command register. It does not affect upstream MSIs,
upstream PCI INTA-INTD assert and de-assert messages.
9
0h
RO
FB2B: Fast Back-to-Back Enable: Not Applicable or Implemented. Hardwired to 0.
8
0h
RW
SERRE: SERR# Message Enable: Controls the root port's SERR# messaging. The
Processor communicates the SERR# condition by sending an SERR message to the
PCH. This bit, when set, enables reporting of non-fatal and fatal errors detected by the
device to the Root Complex. Note that errors are reported if enabled either through
this bit or through the PCI-Express specific bits in the Device Control Register.
In addition, for Type 1 configuration space header devices, this bit, when set, enables
transmission by the primary interface of ERR_NONFATAL and ERR_FATAL error
messages forwarded from the secondary interface. This bit does not affect the
transmission of forwarded ERR_COR messages.
0: The SERR message is generated by the root port only under conditions enabled
individually through the Device Control Register.
1: The root port is enabled to generate SERR messages which will be sent to the PCH
for specific root port error conditions generated/detected or received on the secondary
side of the virtual PCI to PCI bridge. The status of SERRs generated is reported in the
PCISTS register.
7
0h
RO
Reserved (RSVD): Reserved.
6
0h
RW
PERRE: Parity Error Response Enable: Controls whether or not the Master Data Parity
Error bit in the PCI Status register can bet set.
0: Master Data Parity Error bit in PCI Status register can NOT be set.
1: Master Data Parity Error bit in PCI Status register CAN be set.
5
0h
RO
VGAPS: VGA Palette Snoop: Not Applicable or Implemented. Hardwired to 0.
4
0h
RO
MWIE: Memory Write and Invalidate Enable: Not Applicable or Implemented.
Hardwired to 0.
3
0h
RO
SCE: Special Cycle Enable: Not Applicable or Implemented. Hardwired to 0.