Specification Sheet
Datasheet, Volume 2 of 2 357
IMGU Registers
§ §
Bit
Range
Default &
Access
Field Name (ID): Description
31:24
0h
RO
DT: Does not apply. Hardwired to 0
23
0h
RO
BPCCE: Does not apply. Hardwired to 0
22
0h
RO
B23: This bit is hardwired to 0
21:16
0h
RO
Reserved (RSVD): Reserved.
15
0h
RO
PMES: This bit is hardwired to 0 to indicate that PME# assertion from D3 (cold) is
disabled.
14:13
0h
RO
DS: These bits are hardwired to zero. The IMGU does not support data register.
12:9
0h
RO
DSEL: These bits are hardwired to zero. The IMGU does not support data register.
8
0h
RO
PMEEN: This bit is hardwired to 0 to indicate that PME# assertion from D3 (cold) is
disabled.
7:4
0h
RO
Reserved (RSVD): Reserved.
3
0h
RO
NSR:
1: Devices transitioning from D3hot to D0 because of PowerState commands do not
perform an internal reset. Configuration context is preserved. Upon transition from the
D3hot to the D0 initialized state, no additional operating system intervention is
required to preserve Configuration Context beyond writing the PowerState bits. The
processor does not reset so this is 1 and the context is preserved. The IMGU software
developers prefer this setting, which is also natural for hardware.
0: Devices do perform an internal reset upon transitioning from D3hot to D0 via
software control of the PowerState bits. Configuration context is lost when performing
the soft reset. Upon transition from the D3hot to the D0 state, full reinitialization
sequence is needed to return the device to D0 initialized. Regardless of this bit,
devices that transition from D3hot to D0 by a system or bus segment reset will return
to the device state D0 uninitialized with only PME context preserved if PME is
supported and enabled.
2
0h
RO
Reserved (RSVD): Reserved.
1:0
0h
ROV
PS: This field indicates the current power state of the IMGU and can be used to set the
IMGU into a new power state. If software attempts to write an unsupported state to
this field, the write operation should complete normally on the bus, but the data is
discarded and no state change occurs.
Bits[1:0] Power state
00: D0 Default
01: D1 Not Supported
10: D2 Not Supported
11: D3