Specification Sheet

Datasheet, Volume 2 of 2 43
Processor Configuration Register Definitions and Address Ranges
2.7.5 Memory Re-claim Background
The following are examples of Memory Mapped IO devices that are typically located
below 4 GB:
• High BIOS
• TSEG
• GFX stolen
• GTT stolen
• XAPIC
• Local APIC
• MSI Interrupts
• Mbase/Mlimit
• Pmbase/PMlimit
• Memory Mapped IO space that supports only 32B addressing
The processor provides the capability to re-claim the physical memory overlapped by
the Memory Mapped IO logical address space. The MCH re-maps physical memory from
the Top of Low Memory (TOLUD) boundary up to the 4 GB boundary to an equivalent
sized logical address range located just below the Intel ME stolen memory.
2.7.6 Indirect Accesses to MCHBAR Registers
Similar to prior chipsets, MCHBAR registers can be indirectly accessed using:
• Direct MCHBAR access decode:
— Cycle to memory from processor
— Hits MCHBAR base, AND
— MCHBAR is enabled, AND
— Within MMIO space (above and below 4 GB)
• GTTMMADR (10000h – 13FFFh) range -> MCHBAR decode:
— Cycle to memory from processor, AND
— Device 2 (Processor Graphics) is enabled, AND
— Memory accesses for device 2 is enabled, AND
— Targets GFX MMIO Function 0, AND
— MCHBAR is enabled or cycle is a read. If MCHBAR is disabled, only read access
is allowed.
• MCHTMBAR -> MCHBAR (Thermal Monitor)
— Cycle to memory from processor, AND
— Targets MCHTMBAR base
• IOBAR -> GTTMMADR -> MCHBAR.
— Follows IOBAR rules. See GTTMMADR information above as well.