Specification Sheet

Datasheet, Volume 2 of 2 355
IMGU Registers
11.23 Advanced Features Control (AFCTL)—Offset A4h
Advanced Features Control
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
15:10
0h
RO
Reserved (RSVD): Reserved.
9
1h
RO
FLR_CAP: Indicates support for Function Level Reset (FLR)
8
1h
RO
TXP_CAP: Indicates support for the Transactions Pending bit
7:0
6h
RO
CAP_LEN: The Advanced Features capability structure requires 6 bytes of
configuration space
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:5, F:0] + A4h
7 4 0
0 0 0 0 0 0 0 0
RSVD
INIT_FLR
Bit
Range
Default &
Access
Field Name (ID): Description
7:1
0h
RO
Reserved (RSVD): Reserved.
0
0h
RW1S
INIT_FLR: Initiate Function Level Reset - A write of 1 initiates Function Level Reset
(FLR).
FLR requirements are defined in the PCI Express Base Specification.
Registers and state information that do not apply to conventional PCI are exempt from
the FLR requirements given there. Once written 1, FLR will be initiated. During FLR, a
read will return 1`s - reads abort.
Once FLR completes, hardware will clear the bit to 0.