Specification Sheet

Datasheet, Volume 2 of 2 353
IMGU Registers
11.19 Message Address (MA)—Offset 98h
Access Method
Default: 0h
11.20 Message Data (MD)—Offset 9Ch
Access Method
Default: 0h
Type: CFG
(Size: 32 bits)
Offset: [B:0, D:5, F:0] + 98h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MA
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0h
RW
MA: Used by system software to assign an MSI address to the device. The device
handles an MSI by writing the padded contents of the MD register to this address. This
is the higher 4byte bits of the MSI address.
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:5, F:0] + 9Ch
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MD
Bit
Range
Default &
Access
Field Name (ID): Description
15:0
0h
RW
MD: Base message data pattern assigned by system software and used to handle an
MSI from the device.
When the device should generate an interrupt request, it writes a 32-bit value to the
memory address specified in the MA register. The upper 16 bits are always set to 0.
The lower 16 bits are supplied by this register.