Specification Sheet

Datasheet, Volume 2 of 2 351
IMGU Registers
11.16 Message Signaled Interrupts Capability ID
(MSI)—Offset 90h
When a device supports MSI it can generate an interrupt request to the processor by
writing a predefined data item (a message) to a predefined memory address. The
reporting of the existence of this capability can be disabled by setting MSICH (CAPL[0]
@ 7Fh). In that case walking this linked list will skip this capability and instead go
directly to the PCI PM capability.
Access Method
Default: A005h
11.17 Message Control (MC)—Offset 92h
System software can modify bits in this register, but the device is prohibited from doing
so. If the device writes the same message multiple times, only one of those messages
is guaranteed to be serviced. If all of them should be serviced, the device should not
generate the same message again until the driver services the earlier one.
Access Method
Default: 80h
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:5, F:0] + 90h
15 12 8 4 0
1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1
PNCAP
CID
Bit
Range
Default &
Access
Field Name (ID): Description
15:8
A0h
RO
PNCAP: This contains a pointer to the next item in the capabilities list.
7:0
5h
RO
CID: Value of 05h identifies this linked list item (capability structure) as being for MSI
registers.
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:5, F:0] + 92h
15 12 8 4 0
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
RSVD
AC64
MME
MMC
MSIEN