Specification Sheet

Datasheet, Volume 2 of 2 347
IMGU Registers
11.9 Built In Self Test (BIST)—Offset Fh
This register is used for control and status of Built In Self Test (BIST).
Access Method
Default: 0h
11.10 IMGU Memory Mapped Register Range Base
(IMGBAR)—Offset 10h
This is the base address for the IMGU Memory Mapped space.
Access Method
Default: 4h
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
0h
RO
HDR: This field always returns 0 to indicate that the IMGU device is a single function
device with standard header layout.
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:5, F:0] + Fh
7 4 0
0 0 0 0 0 0 0 0
BIST
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
0h
RO
BIST: BIST is not supported. This register is hardwired to 0.
Type: CFG
(Size: 64 bits)
Offset: [B:0, D:5, F:0] + 10h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
RSVDRW
IMGBA
ADM
PM MT
MIOS