Specification Sheet

IMGU Registers
346 Datasheet, Volume 2 of 2
11.7 Master Latency Timer (MLT)—Offset Dh
The IMGU Device does not support the programmability of the master latency timer
because it does not perform bursts.
Access Method
Default: 0h
11.8 Header Type (HDR)—Offset Eh
This register identifies the header layout of the configuration space. No physical
register exists at this location.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
0h
RO
CLS: This field is hardwired to 0.
The IMGU as a PCI compliant master does not use the Memory Write and Invalidate
command and, in general, does not perform operations based on cache line size.
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:5, F:0] + Dh
7 4 0
0 0 0 0 0 0 0 0
MLT
Bit
Range
Default &
Access
Field Name (ID): Description
7:0
0h
RO
MLT: The IMGU Device does not support perform bursts.
Type: CFG
(Size: 8 bits)
Offset: [B:0, D:5, F:0] + Eh
7 4 0
0 0 0 0 0 0 0 0
HDR