Specification Sheet

IMGU Registers
344 Datasheet, Volume 2 of 2
11.4 PCI Status (PCISTS)—Offset 6h
This register reports the status of the IMGU.
Access Method
Default: 10h
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:5, F:0] + 6h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
DPE
SSE
RURS
RCAS
STAS
DEVT
DPD
FB2B
RSVD
CAP66
CLIST
IS
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
15
0h
RO
DPE: The IMGU does not implement this bit and it is hardwired to a 0. Writes to this
bit position have no effect.
14
0h
RO
SSE: The IMGU never asserts SERR#, therefore this bit is hardwired to 0.
13
0h
RW1C
RURS: if the IMGU receive UR on a valid completion it set this bit
12
0h
RW1C
RCAS: if the IMGU receive CA on a valid completion it set this bit
11
0h
RO
STAS: The IMGU Device will not generate a Target Abort. This bit is not implemented
and is hardwired to a 0
10:9
0h
RO
DEVT: These bits are hardwired to 0. Device 5 does not physically connect to PCI_A.
8
0h
RO
DPD: PERR signaling and messaging are not implemented by the IMGU therefore this
bit is hardwired to 0.
7
0h
RO
FB2B: Not Applicable or Implemented. Hardwired to 0.
6
0h
RO
Reserved (RSVD): Reserved.
5
0h
RO
CAP66: Not Applicable or Implemented. Hardwired to 0.
4
1h
RO
CLIST: Indicates that a capabilities list is present. Hardwired to 1.
3
0h
RO_V
IS: Reflects the state of the INTA# signal at the input of the enable/disable circuit.
This bit is set by HW to 1 when the INTA# is asserted.
This bit is reset by HW to 0 after the interrupt is cleared (independent of the state of
the Interrupt Disable bit in the 0.5.0.PCICMD register).
2:0
0h
RO
Reserved (RSVD): Reserved.