Specification Sheet

Datasheet, Volume 2 of 2 343
IMGU Registers
11.3 PCI Command (PCICMD)—Offset 4h
This 16-bit register provides basic control over the IMGU device's ability to respond to
PCI cycles. The PCICMD Register in the IMGU disables the IMGU PCI compliant master
accesses to main memory.
Access Method
Default: 0h
Type: CFG
(Size: 16 bits)
Offset: [B:0, D:5, F:0] + 4h
15 12 8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
INTDIS
FB2B
SERRE
ADSTEP
PERRE
VGAPS
MWIE
SCE
BME
MAE
IOAE
Bit
Range
Default &
Access
Field Name (ID): Description
15:11
0h
RO
Reserved (RSVD): Reserved.
10
0h
RW
INTDIS: This bit disables the device from asserting INTA#.
0b: Enable the assertion of this device's INTA# signal.
1b: Disable the assertion of this device's INTA# signal.
9
0h
RO
FB2B: Not Applicable or Implemented. Hardwired to 0.
8
0h
RO
SERRE: Not Implemented. Hardwired to 0.
7
0h
RO
ADSTEP: Not Implemented. Hardwired to 0.
6
0h
RO
PERRE: Not Implemented. Hardwired to 0.
Since the IMGU Device belongs to the category of devices that does not corrupt
programs or data in system memory or hard drives, the Device ignores any parity
error that it detects and continues with normal operation.
5
0h
RO
VGAPS: Not Applicable or Implemented. Hardwired to 0.
4
0h
RO
MWIE: Not Applicable or Implemented. Hardwired to 0.
3
0h
RO
SCE: Not Applicable or Implemented. Hardwired to 0.
2
0h
RW
BME:
0: Disable IMGU Device bus mastering.
1: Enable the IMGU Device to function as a PCI compliant master.
1
0h
RW
MAE: The IMGU Device will allow access to MMIO registers when this is set to '1'. else,
Rd will be answered with CA, writes will be dropped
0
0h
RO
IOAE: This bit is hardwired to 0. The IMGU Device does not implement this bit and it is
hardwired to a 0.