Specification Sheet
Datasheet, Volume 2 of 2 335
VC0PREMAP Registers
10.28 Fault Recording Low Register (FRCDL)—Offset
400h
Register to record fault information when primary fault logging is active. Hardware
reports the number and location of fault recording registers through the Capability
register. This register is relevant only for primary fault logging.
This register is sticky and can be cleared only through power good reset or by software
clearing the RW1C fields by writing a 1.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
63:39
0h
RO
Reserved (RSVD): Reserved.
38:12
0h
RW_L
IRTA: This field points to the base of 4KB aligned interrupt remapping table.
Hardware ignores and does not implement bits 63:HAW, where HAW is the host
address width.
Reads of this field returns value that was last programmed to it.
11
0h
ROV
EIME: This field is used by hardware on Intel®64 platforms as follows:
0: xAPIC mode is active. Hardware interprets only low 8-bits of Destination-ID field in
the IRTEs. The high 24-bits of the Destination-ID field are treated as reserved.
1: x2APIC mode is active. Hardware interprets all 32-bits of Destination-ID field in the
IRTEs.
This field is implemented as RsvdZ on implementations reporting Extended Interrupt
Mode (EIM) field as Clear in Extended Capability register.
10:4
0h
RO
Reserved (RSVD): Reserved.
3:0
0h
RW_L
S: This field specifies the size of the interrupt remapping table. The number of entries
in the interrupt remapping table is 2^(X+1), where X is the value programmed in this
field.
Type: MEM
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 400h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FI
RSVD