Specification Sheet
VC0PREMAP Registers
334 Datasheet, Volume 2 of 2
10.26 Invalidation Event Upper Address Register
(IEUADDR)—Offset ACh
Register specifying the Invalidation Event interrupt message upper address.
Access Method
Default: 0h
10.27 Interrupt Remapping Table Address Register
(IRTA)—Offset B8h
Register providing the base address of Interrupt remapping table. This register is
treated as RsvdZ by implementations reporting Interrupt Remapping (IR) as not
supported in the Extended Capability register.
Access Method
Default: 0h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + ACh
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MUA
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0h
RW_L
MUA: Hardware implementations supporting Queued Invalidations and Extended
Interrupt Mode are required to implement this register.
Hardware implementations not supporting Queued Invalidations or Extended Interrupt
Mode may treat this field as RsvdZ.
Type: MEM
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + B8h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
IRTA
EIME
RSVD
S