Specification Sheet
VC0PREMAP Registers
332 Datasheet, Volume 2 of 2
10.24 Invalidation Event Data Register (IEDATA)—
Offset A4h
Register specifying the Invalidation Event interrupt message data.
This register is treated as RsvdZ by implementations reporting Queued Invalidation
(QI) as not supported in the Extended Capability register.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
31
1h
RW_L
IM:
0: No masking of interrupt. When a invalidation event condition is detected, hardware
issues an interrupt message (using the Invalidation Event Data & Invalidation Event
Address register values).
1: This is the value on reset. Software may mask interrupt message generation by
setting this field. Hardware is prohibited from sending the interrupt message when this
field is Set.
30
0h
ROV
IP: Hardware sets the IP field whenever it detects an interrupt condition. Interrupt
condition is defined as:
• An Invalidation Wait Descriptor with Interrupt Flag (IF) field Set completed,
setting the IWC field in the Invalidation Completion Status register.
• If the IWC field in the Invalidation Completion Status register was already Set at
the time of setting this field, it is not treated as a new interrupt condition.
The IP field is kept Set by hardware while the interrupt message is held pending. The
interrupt message could be held pending due to interrupt mask (IM field) being Set, or
due to other transient hardware conditions. The IP field is cleared by hardware as soon
as the interrupt message pending condition is serviced. This could be due to either:
• Hardware issuing the interrupt message due to either change in the transient
hardware condition that caused interrupt message to be held pending or due to
software clearing the IM field.
• Software servicing the IWC field in the Invalidation Completion Status register.
29:0
0h
RO
Reserved (RSVD): Reserved.
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + A4h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EIMD
IMD