Specification Sheet

Datasheet, Volume 2 of 2 331
VC0PREMAP Registers
10.23 Invalidation Event Control Register (IECTL)—
Offset A0h
Register specifying the invalidation event interrupt control bits.
This register is treated as RsvdZ by implementations reporting Queued Invalidation
(QI) as not supported in the Extended Capability register.
Access Method
Default: 80000000h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
IWC
Bit
Range
Default &
Access
Field Name (ID): Description
31:1
0h
RO
Reserved (RSVD): Reserved.
0
0h
RW1CS
IWC: Indicates completion of Invalidation Wait Descriptor with Interrupt Flag (IF) field
Set. Hardware implementations not supporting queued invalidations implement this
field as RsvdZ.
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + A0h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IM
IP
RSVD