Specification Sheet
VC0PREMAP Registers
330 Datasheet, Volume 2 of 2
10.21 Invalidation Queue Address Register (IQA)—
Offset 90h
Register to configure the base address and size of the invalidation queue. This register
is treated as RsvdZ by implementations reporting Queued Invalidation (QI) as not
supported in the Extended Capability register.
Access Method
Default: 0h
10.22 Invalidation Completion Status Register (ICS)—
Offset 9Ch
Register to report completion status of invalidation wait descriptor with Interrupt Flag
(IF) Set.
This register is treated as RsvdZ by implementations reporting Queued Invalidation
(QI) as not supported in the Extended Capability register.
Access Method
Default: 0h
Type: MEM
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 90h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
IQA
RSVD
QS
Bit
Range
Default &
Access
Field Name (ID): Description
63:39
0h
RO
Reserved (RSVD): Reserved.
38:12
0h
RW_L
IQA: This field points to the base of 4KB aligned invalidation request queue. Hardware
ignores and does not implement bits 63:HAW, where HAW is the host address width.
Reads of this field return the value that was last programmed to it.
11:3
0h
RO
Reserved (RSVD): Reserved.
2:0
0h
RW_L
QS: This field specifies the size of the invalidation request queue. A value of X in this
field indicates an invalidation request queue of (2^X) 4KB pages. The number of
entries in the invalidation queue is 2^(X + 8).
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 9Ch