Specification Sheet

ManualsBrandsINTEL ManualsPC ComponentsWOF processor Core i7 i7-7700K 4 x 4.2 GHz Q

Datasheet, Volume 2 of 2 3

Contents

1 Introduction ............................................................................................................ 16

2 Processor Configuration Register Definitions and Address Ranges........................... 17

2.1 Register Terminology .........................................................................................17

2.2 PCI Devices and Functions ..................................................................................18

2.3 System Address Map ......................................................................................... 20

2.4 Legacy Address Range ....................................................................................... 23

2.4.1 DOS Range (0h – 9_FFFFh) ..................................................................... 24

2.4.2 Legacy Video Area / Compatible SMRAM Area (A_0000h – B_FFFFh) .............24

2.4.3 Legacy Video Area .................................................................................. 24

2.4.4 Monochrome Adapter (MDA) Range .......................................................... 24

2.4.5 Compatible SMRAM Address Range ........................................................... 24

2.4.6 Programmable Attribute Map (PAM) (C_0000h – F_FFFFh) ........................... 24

2.5 Main Memory Address Range (1 MB – TOLUD).......................................................26

2.5.1 ISA Hole (15 MB –16 MB) ........................................................................ 27

2.5.2 1 MB to TSEGMB .................................................................................... 27

2.5.3 TSEG .................................................................................................... 27

2.5.4 Protected Memory Range (PMR) - (programmable) .....................................27

2.5.5 DRAM Protected Range (DPR) .................................................................. 28

2.5.6 Pre-allocated Memory ............................................................................. 28

2.6 PCI Memory Address Range (TOLUD – 4 GB)......................................................... 29

2.6.1 APIC Configuration Space (FEC0_0000h – FECF_FFFFh)...............................31

2.6.2 HSEG (FEDA_0000h – FEDB_FFFFh).......................................................... 31

2.6.3 MSI Interrupt Memory Space (FEE0_0000h – FEEF_FFFFh) ..........................31

2.6.4 High BIOS Area...................................................................................... 31

2.7 Main Memory Address Space (4 GB to TOUUD)...................................................... 32

2.7.1 Top of Memory (TOM) ............................................................................. 32

2.7.2 Top of Upper Usable DRAM (TOUUD)......................................................... 32

2.7.3 Top of Low Usable DRAM (TOLUD) ............................................................32

2.7.4 TSEG_BASE........................................................................................... 32

2.7.5 Memory Re-claim Background ..................................................................33

2.7.6 Indirect Accesses to MCHBAR Registers ..................................................... 33

2.7.7 Memory Remapping................................................................................ 34

2.7.8 Hardware Remap Algorithm ..................................................................... 34

2.8 PCI Express* Configuration Address Space ........................................................... 34

2.9 Graphics Memory Address Ranges .......................................................................34

2.9.1 IOBAR Mapped Access to Device 2 MMIO Space.......................................... 35

2.9.2 Trusted Graphics Ranges ......................................................................... 35

2.10 System Management Mode (SMM) .......................................................................35

2.11 SMM and VGA Access Through GTT TLB................................................................36

2.12 Intel® Management Engine (Intel® ME) Stolen Memory Accesses............................ 36

2.13 I/O Address Space.............................................................................................36

2.13.1 PCI Express* I/O Address Mapping ........................................................... 37

2.14 Direct Media Interface (DMI) Interface Decode Rules..............................................38

2.14.1 DMI Accesses to the Processor that Cross Device Boundaries........................ 38

2.14.2 Traffic Class (TC) / Virtual Channel (VC) Mapping Details .............................39

2.15 PCI Express* Interface Decode Rules ................................................................... 41

2.15.1 TC/VC Mapping Details............................................................................ 41

2.16 Legacy VGA and I/O Range Decode Rules ............................................................. 41

2.17 I/O Mapped Registers .......................................................................................45