Specification Sheet

Datasheet, Volume 2 of 2 325
VC0PREMAP Registers
Default: 0h
10.16 Protected Low-Memory Limit Register
(PLMLIMIT)—Offset 6Ch
Register to set up the limit address of DMA-protected low-memory region below 4GB.
This register should be set up before enabling protected memory through PMEN_REG,
and should not be updated when protected memory regions are enabled.
This register is always treated as RO for implementations not supporting protected low
memory region (PLMR field reported as Clear in the Capability register).
The alignment of the protected low memory region limit depends on the number of
reserved bits (N:0) of this register. Software may determine N by writing all 1's to this
register, and finding most significant zero bit position with 0 in the value read back from
the register. Bits N:0 of the limit register is decoded by hardware as all 1s.
The Protected low-memory base and limit registers functions as follows:
• Programming the protected low-memory base and limit registers with the same
value in bits 31:(N+1) specifies a protected low-memory region of size 2^(N+1)
bytes.
• Programming the protected low-memory limit register with a value less than the
protected low-memory base register disables the protected low-memory region.
Software should not modify this register when protected memory regions are enabled
(PRS field Set in PMEN_REG).
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PLMB
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
31:20
0h
RW
PLMB: This register specifies the base of protected low-memory region in system
memory.
19:0
0h
RO
Reserved (RSVD): Reserved.