Specification Sheet

Datasheet, Volume 2 of 2 323
VC0PREMAP Registers
10.14 Protected Memory Enable Register (PMEN)—
Offset 64h
Register to enable the DMA-protected memory regions setup through the PLMBASE,
PLMLIMT, PHMBASE, PHMLIMIT registers. This register is always treated as RO for
implementations not supporting protected memory regions (PLMR and PHMR fields
reported as Clear in the Capability register).
Protected memory regions may be used by software to securely initialize remapping
structures in memory. To avoid impact to legacy BIOS usage of memory, software is
recommended to not overlap protected memory regions with any reserved memory
regions of the platform reported through the Reserved Memory Region Reporting
(RMRR) structures.
Access Method
Default: 0h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FLA FLS
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
63:12
0h
RO
FLA: This field specifies the base of 4KB aligned fault-log region in system memory.
Hardware ignores and does not implement bits 63:HAW, where HAW is the host
address width.
Software specifies the base address and size of the fault log region through this
register, and programs it in hardware through the SFL field in the Global Command
register. When implemented, reads of this field return the value that was last
programmed to it.
11:9
0h
RO
FLS: This field specifies the size of the fault log region pointed by the FLA field. The
size of the fault log region is 2^X * 4KB, where X is the value programmed in this
register.
When implemented, reads of this field return the value that was last programmed to it.
8:0
0h
RO
Reserved (RSVD): Reserved.
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 64h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EPM
RSVD
PRS