Specification Sheet

Datasheet, Volume 2 of 2 39
Processor Configuration Register Definitions and Address Ranges
2.6 PCI Memory Address Range (TOLUD – 4 GB)
Top of Low Usable DRAM (TOLUD) – TOLUD is restricted to 4 GB memory (A[31:20]),
but the System Agent may support up to a much higher capacity, which is limited by
DRAM pins.
This address range from the top of low usable DRAM (TOLUD) to 4 GB is normally
mapped to the DMI Interface.
Device 0 exceptions are:
1. Addresses decoded to the egress port registers (PXPEPBAR)
2. Addresses decoded to the memory mapped range for internal MCH registers
(MCHBAR)
3. Addresses decoded to the registers associated with the MCH/PCH Serial
Interconnect (DMI) register memory range. (DMIBAR)
For each PCI Express* port, there are two exceptions to this rule:
4. Addresses decoded to the PCI Express Memory Window defined by the MBASE,
MLIMIT registers are mapped to PCI Express.
5. Addresses decoded to the PCI Express prefetchable Memory Window defined by the
PMBASE, PMLIMIT registers are mapped to PCI Express.
In Processor Graphics configurations, there are exceptions to this rule:
6. Addresses decode to the Processor Graphics translation window (GMADR)
7. Addresses decode to the Processor Graphics translation table or Processor Graphics
registers. (GTTMMADR)
In an Intel VT enable configuration, there are exceptions to this rule:
8. Addresses decoded to the memory mapped window to Graphics Intel VT remap
engine registers (GFXVTBAR)
9. Addresses decoded to the memory mapped window to DMI VC1 Intel VT remap
engine registers (DMIVC1BAR)
10. Addresses decoded to the memory mapped window to PEG/DMI VC0 Intel VT
remap engine registers (VTDPVC0BAR)
11. TCm accesses (to Intel ME stolen memory) from PCH do not go through Intel VT
remap engines.
Some of the MMIO Bars may be mapped to this range or to the range above TOUUD.
There are sub-ranges within the PCI memory address range defined as APIC
Configuration Space, MSI Interrupt Space, and High BIOS address range. The
exceptions listed above for Processor Graphics and the PCI Express ports should NOT
overlap with these ranges.