Specification Sheet

Datasheet, Volume 2 of 2 313
VC0PREMAP Registers
26
0h
WO
QIE: This field is valid only for implementations supporting queued invalidations.
Software writes to this field to enable or disable queued invalidations.
0: Disable queued invalidations.
1: Enable use of queued invalidations.
Hardware reports the status of queued invalidation enable operation through QIES
field in the Global Status register.
The value returned on a read of this field is undefined.
25
0h
WO
IRE: This field is valid only for implementations supporting interrupt remapping.
0: Disable interrupt-remapping hardware
1: Enable interrupt-remapping hardware
Hardware reports the status of the interrupt remapping enable operation through the
IRES field in the Global Status register.
There may be active interrupt requests in the platform when software updates this
field. Hardware should enable or disable interrupt-remapping logic only at
deterministic transaction boundaries, so that any in-flight interrupts are either subject
to remapping or not at all.
Hardware implementations should drain any in-flight interrupts requests queued in the
Root-Complex before completing the interrupt-remapping enable command and
reflecting the status of the command through the IRES field in the Global Status
register.
The value returned on a read of this field is undefined.
24
0h
WO
SIRTP: This field is valid only for implementations supporting interrupt-remapping.
Software sets this field to set/update the interrupt remapping table pointer used by
hardware. The interrupt remapping table pointer is specified through the Interrupt
Remapping Table Address (IRTA_REG) register.
Hardware reports the status of the 'Set Interrupt Remap Table Pointer' operation
through the IRTPS field in the Global Status register.
The 'Set Interrupt Remap Table Pointer' operation should be performed before
enabling or re-enabling (after disabling) interrupt-remapping hardware through the
IRE field.
After a 'Set Interrupt Remap Table Pointer' operation, software should globally
invalidate the interrupt entry cache. This is required to ensure hardware uses only the
interrupt-remapping entries referenced by the new interrupt remap table pointer, and
not any stale cached entries.
While interrupt remapping is active, software may update the interrupt remapping
table pointer through this field. However, to ensure valid in-flight interrupt requests
are deterministically remapped, software should ensure that the structures referenced
by the new interrupt remap table pointer are programmed to provide the same
remapping results as the structures referenced by the previous interrupt remap table
pointer.
Clearing this bit has no effect. The value returned on a read of this field is undefined.
23
0h
WO
CFI: This field is valid only for Intel®64 implementations supporting interrupt-
remapping.
Software writes to this field to enable or disable Compatibility Format interrupts on
Intel®64 platforms. The value in this field is effective only when interrupt-remapping
is enabled and Extended Interrupt Mode (x2APIC mode) is not enabled.
0: Block Compatibility format interrupts.
1: Process Compatibility format interrupts as pass-through (bypass interrupt
remapping).
Hardware reports the status of updating this field through the CFIS field in the Global
Status register.
The value returned on a read of this field is undefined.
22:0
0h
RO
Reserved (RSVD): Reserved.
Bit
Range
Default &
Access
Field Name (ID): Description