Specification Sheet

VC0PREMAP Registers
310 Datasheet, Volume 2 of 2
28
0h
RO
PASID:
0: Hardware does not support process address space IDs.
1: Hardware supports Process Address Space IDs.
27
0h
RO
DIS:
0: Hardware does not support deferred invalidations of IOTLB and Device-TLB.
1: Hardware supports deferred invalidations of IOTLB and Device-TLB.
26
0h
RO
NEST:
0: Hardware does not support nested translations.
1: Hardware supports nested translations.
25
0h
RO
MTS:
0: Hardware does not support Memory Type
1: Hardware supports Memory Type
24
0h
RO
ECS:
0: Hardware does not support extended-root-entries and Extended Context-Entries
1: Hardware supports extended-root-entries and Extended Context-Entries
23:20
Fh
RO
MHMV: The value in this field indicates the maximum supported value for the Handle
Mask (HM) field in the interrupt entry cache invalidation descriptor (iec_inv_dsc).
This field is valid only when the IR field in Extended Capability register is reported as
Set.
19:18
0h
RO
Reserved (RSVD): Reserved.
17:8
50h
RO
IRO: This field specifies the offset to the IOTLB registers relative to the register base
address of this remapping hardware unit.
If the register base address is X, and the value reported in this field is Y, the address
for the first IOTLB invalidation register is calculated as X+(16*Y).
7
1h
ROV
SC:
0: Hardware does not support 1-setting of the SNP field in the page-table entries.
1: Hardware supports the 1-setting of the SNP field in the page-table entries.
6
1h
ROV
PT: 0: Hardware does not support pass-through translation type in context entries.
1: Hardware supports pass-through translation type in context entries.
5
0h
RO
Reserved (RSVD): Reserved.
4
1h
ROV
EIM:
0: On Intel®64 platforms, hardware supports only 8-bit APIC-IDs (xAPIC mode).
1: On Intel®64 platforms, hardware supports 32-bit APIC-IDs (x2APIC mode).
This field is valid only on Intel®64 platforms reporting Interrupt Remapping support
(IR field Set).
3
1h
ROV
IR:
0: Hardware does not support interrupt remapping.
1: Hardware supports interrupt remapping.
Implementations reporting this field as Set should also support Queued Invalidation
(QI).
Bit
Range
Default &
Access
Field Name (ID): Description