Specification Sheet

VC0PREMAP Registers
308 Datasheet, Volume 2 of 2
21:16
26h
RO
MGAW: This field indicates the maximum DMA virtual addressability supported by
remapping hardware. The Maximum Guest Address Width (MGAW) is computed as
(N+1), where N is the value reported in this field. For example, a hardware
implementation supporting 48-bit MGAW reports a value of 47 (101111b) in this field.
If the value in this field is X, untranslated and translated DMA requests to addresses
above 2^(x+1)-1 are always blocked by hardware. Translations requests to address
above 2^(x+1)-1 from allowed devices return a null Translation Completion Data
Entry with R=W=0.
Guest addressability for a given DMA request is limited to the minimum of the value
reported through this field and the adjusted guest address width of the corresponding
page-table structure. (Adjusted guest address widths supported by hardware are
reported through the SAGAW field).
Implementations are recommended to support MGAW at least equal to the physical
addressability (host address width) of the platform.
15:13
0h
RO
Reserved (RSVD): Reserved.
12:8
4h
RO
SAGAW: This 5-bit field indicates the supported adjusted guest address widths (which
in turn represents the levels of page-table walks for the 4KB base page size)
supported by the hardware implementation.
A value of 1 in any of these bits indicates the corresponding adjusted guest address
width is supported. The adjusted guest address widths corresponding to various bit
positions within this field are:
0: 30-bit AGAW (2-level page table)
1: 39-bit AGAW (3-level page table)
2: 48-bit AGAW (4-level page table)
3: 57-bit AGAW (5-level page table)
4: 64-bit AGAW (6-level page table)
Software should ensure that the adjusted guest address width used to setup the page
tables is one of the supported guest address widths reported in this field.
7
0h
RO
CM:
0: Not-present and erroneous entries are not cached in any of the renmapping caches.
Invalidations are not required for modifications to individual not present or invalid
entries. However, any modifications that result in decreasing the effective permissions
or partial permission increases require invalidations for them to be effective.
1: Not-present and erroneous mappings may be cached in the remapping caches. Any
software updates to the remapping structures (including updates to "not-present" or
erroneous entries) require explicit invalidation.
Hardware implementations of this architecture should support a value of 0 in this field.
6
1h
RO
PHMR:
0: Indicates protected high-memory region is not supported.
1: Indicates protected high-memory region is supported.
5
1h
RO
PLMR:
0: Indicates protected low-memory region is not supported.
1: Indicates protected low-memory region is supported.
4
0h
RO
RWBF:
0: Indicates no write-buffer flushing is needed to ensure changes to memory-resident
structures are visible to hardware.
1: Indicates software should explicitly flush the write buffers to ensure updates made
to memory-resident remapping structures are visible to hardware.
3
0h
RO
AFL:
0: Indicates advanced fault logging is not supported. Only primary fault logging is
supported.
1: Indicates advanced fault logging is supported.
2:0
2h
RO
ND: 000b: Hardware supports 4-bit domain-ids with support for up to 16 domains.
001b: Hardware supports 6-bit domain-ids with support for up to 64 domains.
010b: Hardware supports 8-bit domain-ids with support for up to 256 domains.
011b: Hardware supports 10-bit domain-ids with support for up to 1024 domains.
100b: Hardware supports 12-bit domain-ids with support for up to 4K domains.
100b: Hardware supports 14-bit domain-ids with support for up to 16K domains.
110b: Hardware supports 16-bit domain-ids with support for up to 64K domains.
111b: Reserved.
Bit
Range
Default &
Access
Field Name (ID): Description