Specification Sheet

Processor Configuration Register Definitions and Address Ranges
38 Datasheet, Volume 2 of 2
To optimally support platform configurations supporting varying amounts of main
memory, the protected memory region is defined as two non-overlapping regions:
• Protected Low-memory Region: This is defined as the protected memory region
below 4 GB to hold the MVMM code/private data, and the initial DMA-remapping
structures that control DMA to host physical addresses below 4 GB. DMA-
remapping hardware implementations on platforms supporting Intel TXT are
required to support protected low-memory region 5.
• Protected High-memory Region: This is defined as a variable sized protected
memory region above 4 GB, enough to hold the initial DMA-remapping structures
for managing DMA accesses to addresses above 4 GB. DMA-remapping hardware
implementations on platforms supporting Intel TXT are required to support
protected high-memory region 6, if the platform supports main memory above
4 GB.
Once the protected low/high memory region registers are configured, bus master
protection to these regions is enabled through the Protected Memory Enable register.
For platforms with multiple DMA-remapping hardware units, each of the DMA-
remapping hardware units should be configured with the same protected memory
regions and enabled.
2.5.5 DRAM Protected Range (DPR)
This protection range only applies to DMA accesses and GMADR translations. It serves a
purpose of providing a memory range that is only accessible to processor streams. The
range just below TSEGMB is protected from DMA accesses.
The DPR range works independent of any other range, including the PMRC checks in
Intel VT-d. It occurs post any Intel VT-d translation. Therefore, incoming cycles are
checked against this range after the Intel VT-d translation and faulted if they hit this
protected range, even if they passed the Intel VT-d translation.
The system will set up:
• 0 to (TSEG_BASE – DPR size – 1) for DMA traffic
• TSEG_BASE to (TSEG_BASE – DPR size) as no DMA.
After some time, software could request more space for not allowing DMA. It will get
some more pages and make sure there are no DMA cycles to the new region. DPR size
is changed to the new value. When it does this, there should not be any DMA cycles
going to DRAM to the new region.
If there were cycles from a rogue device to the new region, then those cycles could use
the previous decode until the new decode can ensure PV. No flushing of cycles is
required.
All upstream cycles from 0 to (TSEG_BASE – 1 – DPR size), and not in the legacy holes
(VGA), are decoded to DRAM.
2.5.6 Pre-allocated Memory
Voids of physical addresses that are not accessible as general system memory and
reside within the system memory address range (< TOLUD) are created for SMM-mode,
legacy VGA graphics compatibility, and GFX GTT stolen memory. It is the
responsibility of BIOS to properly initialize these regions.