Specification Sheet

GFXVTBAR Registers
302 Datasheet, Volume 2 of 2
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13
0h
RW_L
L1DIS:
1: L1 TLB is disabled, and each GPA request that looks up the L1 will result in a miss.
0: Normal mode (default). L1 is enabled.
12
0h
RW_L
L0DIS:
1: L0 TLB is disabled, and each GPA request that looks up the L0 will result in a miss.
0: Normal mode (default). L0 is enabled.
11
0h
RW_L
CCDIS:
1: Context Cache is disabled. Each GPA request results in a miss and will request a
root walk.
0: Normal mode (default). Context Cache is enabled.
10:2
0h
RO
Reserved (RSVD): Reserved.
1
0h
RO
GLBIOTLBINV: This bit controls the IOTLB Invalidation behavior of the DMA remap
engine. When this bit is set, any type of IOTLB Invalidation will be promoted to Global
IOTLB Invalidation. This promotion applies to both register-based invalidation and
queued invalidation.
0
0h
RO
GLBCTXTINV: This bit controls the Context Invalidation behavior of the DMA remap
engine. When this bit is set, any type of Context Invalidation will be promoted to
Global Context Invalidation. This promotion applies to both register-based invalidation
and queued invalidation.
Bit
Range
Default &
Access
Field Name (ID): Description