Specification Sheet

Datasheet, Volume 2 of 2 301
GFXVTBAR Registers
8.33 DMA Remap Engine Policy Control (UARCHDIS)—
Offset FF4h
This register contains all micro-architectural disables and defeatures for the graphics
DMA remap engine.
Access Method
Default: 100000h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + FF4h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
NO_TLBLKUP_PEND
IQ_COH_DIS
L3_HIT2PEND_DIS L2_HIT2PEND_DIS L1_HIT2PEND_DIS L0_HIT2PEND_DIS
CC_HIT2PEND_DIS
L3DIS L2DIS L1DIS L0DIS
CCDIS
RSVD
GLBIOTLBINV
GLBCTXTINV
Bit
Range
Default &
Access
Field Name (ID): Description
31:23
0h
RO
Reserved (RSVD): Reserved.
22
0h
RW_L
NO_TLBLKUP_PEND: When this bit is set, all entries which hit to pending on another
requests TLB allocation in the default engine are not allowed to look up peer aperture
TLBs for a following graphics walk. They should do all page walks (including root and
context) in the Processor Graphics engine.
21
0h
RW_L
IQ_COH_DIS: When this bit is set to 1b, read requests from the Invalidation Queue
are done in a non-coherent manner (no snoops are generated).
20
1h
RW_L
L3_HIT2PEND_DIS: When set, this bit forces a lookup which matches an L3 TLB
entry in PEND state to be treated as a miss without allocation.
19
0h
RO
L2_HIT2PEND_DIS: When set, this bit forces a lookup which matches an L2 TLB
entry in PEND state to be treated as a miss without allocation.
18
0h
RW_L
L1_HIT2PEND_DIS: When set, this bit forces a lookup which matches an L1 TLB
entry in PEND state to be treated as a miss without allocation.
17
0h
RW_L
L0_HIT2PEND_DIS: When set, this bit forces a lookup which matches an L0 TLB
entry in PEND state to be treated as a miss without allocation.
16
0h
RW_L
CC_HIT2PEND_DIS: When set, this bit forces a lookup which matches a context
cache entry in PEND state to be treated as a miss without allocation.
15
0h
RW_L
L3DIS:
1: L3 TLB is disabled, and each GPA request that looks up the L3 will result in a miss.
0: Normal mode (default). L3 is enabled.
14
0h
RO
L2DIS:
1: L2 TLB is disabled, and each GPA request that looks up the L2 will result in a miss.
0: Normal mode (default). L2 is enabled.