Specification Sheet

GFXVTBAR Registers
300 Datasheet, Volume 2 of 2
11
0h
RW_L
DTCAPDIS: This bit allows hiding the Device TLB Capability.
0: ECAP_REG[DT] is determined by its own default value.
1: ECAP_REG[DT] is set to 0b.
10
0h
RW_L
PASIDCAPDIS: This bit allows hiding the PASID Capability.
0: ECAP_REG[PASID] is determined by its own default value.
1: ECAP_REG[PASID] is set to 0b.
9
0h
RW_L
ECSCAPDIS: This bit allows hiding the Extended Context Capability.
0: ECAP_REG[ECS] is determined by its own default value.
1: ECAP_REG[ECS] is set to 0b. Additionally hardware will prevent writing of '1' to
RTADDR_REG.b[11].
8
0h
RO
SCCAPDIS: This bit allows hiding the Snoop Control Capability.
0: ECAP_REG[SC] is determined by its own default value.
1: ECAP_REG[SC] is set to 0b.
7
0h
RW_L
PTCAPDIS: This bit allows hiding the Pass Through Capability.
0: ECAP_REG[PT] is determined by its own default value.
1: ECAP_REG[PT] is set to 0b.
6
0h
RO_KFW
IRCAPDIS: This bit allows hiding the Interrupt Remapping Capability.
0: ECAP_REG[IR] is determined by its own default value.
1: ECAP_REG[IR] is set to 0b.
5
0h
RO_KFW
QICAPDIS: This bit allows hiding the Queued Invalidation Capability.
0: ECAP_REG[QI] is determined by its own default value.
1: ECAP_REG[QI] is set to 0b.
4
0h
RW_L
NESTCAPDIS: This bit allows hiding the Nested Translation Capability.
0: CAP_REG[NEST] is determined by its own default value.
1: CAP_REG[NEST] is set to 0b.
3
0h
RW_L
DISCAPDIS: This bit allows hiding the Deferred Invalidation Support Capability.
0: CAP_REG[DIS] is determined by its own default value.
1: CAP_REG[DIS] is set to 0b.
2
0h
RW_L
PRSCAPDIS: This bit allows hiding the Page Request Capability.
0: CAP_REG[PRS] is determined by its own default value.
1: CAP_REG[PRS] is set to 0b.
1
0h
RW_L
FL1GPCAPDIS: This bit allows hiding the First Level 1G Page Capability.
0: CAP_REG[FL1GP] is determined by its own default value.
1: CAP_REG[FL1GP] is set to 0b.
0
1h
RW_L
SLLPSCAPCTRL: This bit allows enabling/disabling the Super Page Capability.
0: CAP_REG[SLLPS] is set to 0x0 to disable superpages.
1: CAP_REG[SLLPS] is set to 0x3 to enable superpages.
When SLLPSCAPCTRL is set to 0, CAP_REG[SLLPS]=0. If software ignores it and sets
up Super Pages then IMPH will generate VT-d fault.
Bit
Range
Default &
Access
Field Name (ID): Description