Specification Sheet

Datasheet, Volume 2 of 2 299
GFXVTBAR Registers
8.32 DMA Remap Engine Policy Control (ARCHDIS)—
Offset FF0h
This register contains all architectural disables and defeatures for the graphics DMA
remap engine.
Access Method
Default: 1h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + FF0h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
DMAR_LCKDN
DMA_RSRV_CTL
RSVD
NWFSCAPDIS
MTSCAPDIS
EAFSCAPDIS
FL64KPCAPCTRL
DTCAPDIS
PASIDCAPDIS
ECSCAPDIS
SCCAPDIS
PTCAPDIS
IRCAPDIS
QICAPDIS
NESTCAPDIS
DISCAPDIS
PRSCAPDIS
FL1GPCAPDIS
SLLPSCAPCTRL
Bit
Range
Default &
Access
Field Name (ID): Description
31
0h
RW_KL
DMAR_LCKDN: This register bit protects all the DMA remap engine specific policy
configuration registers. Once this bit is set by software all the DMA remap engine
registers within the range 0xF00 to 0xFFC will be read-only. This bit can only be clear
through platform reset.
30
0h
RW_L
DMA_RSRV_CTL: This bit indicates whether Reserved Bit checking is supported or
not (i.e. support for Fault Reason 0xA, 0xB, or 0xC).
0: HW supports reserved field checking in root, context and page translation
structures.
1: HW ignores reserved field checking in root, context, and page translation
structures.
29:16
0h
RO
Reserved (RSVD): Reserved.
15
0h
RW_L
NWFSCAPDIS: This bit allows hiding the NWFS Capability.
0: ECAP_REG[NWFS] is determined by its own default value.
1: ECAP_REG[NWFS] is set to 0b.
14
0h
RW_L
MTSCAPDIS: This bit allows hiding the MTS Capability.
0: ECAP_REG[MTS] is determined by its own default value.
1: ECAP_REG[MTS] is set to 0b.
13
0h
RW_L
EAFSCAPDIS: This bit allows hiding the EAFS Capability.
0: ECAP_REG[EAFS] is determined by its own default value.
1: ECAP_REG[EAFS] is set to 0b.
12
0h
RW_L
FL64KPCAPCTRL: This bit allows hiding the FL64KP Capability.
0: ECAP_REG[FL64KP] is determined by its own default value.
1: ECAP_REG[FL64KP] is set to 0b.