Specification Sheet

Datasheet, Volume 2 of 2 37
Processor Configuration Register Definitions and Address Ranges
2.5.1 ISA Hole (15 MB –16 MB)
The ISA Hole (starting at address F0_0000h) is enabled in the Legacy Access Control
Register in Device 0 configuration space. If no hole is created, the processor will route
the request to DRAM. If a hole is created, the processor will route the request to DMI,
since the request does not target DRAM. These downstream requests will be sent to
DMI (subtractive decoding).
Graphics translated requests to the range will always route to DRAM.
2.5.2 1 MB to TSEGMB
Processor access to this range will be directed to memory, unless the ISA Hole is
enabled.
2.5.3 TSEG
For processor initiated transactions, the processor relies on correct programming of
SMM Range Registers (SMRR) to enforce TSEG protection.
TSEG is below Processor Graphics stolen memory, which is at the Top of Low Usable
physical memory (TOLUD). BIOS will calculate and program the TSEG BASE in Device 0
(TSEGMB), used to protect this region from DMA access. Calculation is:
TSEGMB = TOLUD – DSM SIZE – GSM SIZE – TSEG SIZE
SMM-mode processor accesses to enabled TSEG access the physical DRAM at the same
address.
When the extended SMRAM space is enabled, processor accesses to the TSEG range
without SMM attribute or without WB attribute are handled by the processor as invalid
accesses.
Non-processor originated accesses are not allowed to SMM space. PCI-Express, DMI,
and Processor Graphics originated cycles to enabled SMM space are handled as invalid
cycle type with reads and writes to location C_0000h and byte enables turned off for
writes.
2.5.4 Protected Memory Range (PMR) - (programmable)
For robust and secure launch of the MVMM, the MVMM code and private data need to be
loaded to a memory region protected from bus master accesses. Support for protected
memory region is required for DMA-remapping hardware implementations on platforms
supporting Intel TXT, and is optional for non-Intel TXT platforms. Since the protected
memory region needs to be enabled before the MVMM is launched, hardware should
support enabling of the protected memory region independently from enabling the
DMA-remapping hardware.
As part of the secure launch process, the SINIT-AC module verifies the protected
memory regions are properly configured and enabled. Once launched, the MVMM can
setup the initial DMA-remapping structures in protected memory (to ensure they are
protected while being setup) before enabling the DMA-remapping hardware units.