Specification Sheet
GFXVTBAR Registers
294 Datasheet, Volume 2 of 2
8.28 Fault Recording Low Register (FRCDL)—Offset
400h
Register to record fault information when primary fault logging is active. Hardware
reports the number and location of fault recording registers through the Capability
register. This register is relevant only for primary fault logging.
This register is sticky and can be cleared only through power good reset or by software
clearing the RW1C fields by writing a 1.
Access Method
Default: 0h
8.29 Fault Recording High Register (FRCDH)—Offset
408h
Register to record fault information when primary fault logging is active. Hardware
reports the number and location of fault recording registers through the Capability
register. This register is relevant only for primary fault logging.
This register is sticky and can be cleared only through power good reset or by software
clearing the RW1C fields by writing a 1.
Access Method
Default: 0h
Type: MEM
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 400h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FI
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
63:12
0h
ROSV
FI: When the Fault Reason (FR) field indicates one of the DMA-remapping fault
conditions, bits 63:12 of this field contain the page address in the faulted DMA
request. Hardware treats bits 63:N as reserved (0), where N is the maximum guest
address width (MGAW) supported.
When the Fault Reason (FR) field indicates one of the interrupt-remapping fault
conditions, bits 63:48 of this field indicate the interrupt_index computed for the
faulted interrupt request, and bits 47:12 are cleared.
This field is relevant only when the F field is Set.
11:0
0h
RO
Reserved (RSVD): Reserved.
Type: MEM
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 408h