Specification Sheet
Datasheet, Volume 2 of 2 293
GFXVTBAR Registers
8.27 Interrupt Remapping Table Address Register
(IRTA)—Offset B8h
Register providing the base address of Interrupt remapping table. This register is
treated as RsvdZ by implementations reporting Interrupt Remapping (IR) as not
supported in the Extended Capability register.
Access Method
Default: 0h
Type: MEM
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + B8h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RSVD
IRTA
EIME
RSVD
S
Bit
Range
Default &
Access
Field Name (ID): Description
63:39
0h
RO
Reserved (RSVD): Reserved.
38:12
0h
RW_L
IRTA: This field points to the base of 4KB aligned interrupt remapping table.
Hardware ignores and does not implement bits 63:HAW, where HAW is the host
address width.
Reads of this field returns value that was last programmed to it.
11
0h
ROV
EIME: This field is used by hardware on Intel®64 platforms as follows:
0: xAPIC mode is active. Hardware interprets only low 8-bits of Destination-ID field in
the IRTEs. The high 24-bits of the Destination-ID field are treated as reserved.
1: x2APIC mode is active. Hardware interprets all 32-bits of Destination-ID field in the
IRTEs.
This field is implemented as RsvdZ on implementations reporting Extended Interrupt
Mode (EIM) field as Clear in Extended Capability register.
10:4
0h
RO
Reserved (RSVD): Reserved.
3:0
0h
RW_L
S: This field specifies the size of the interrupt remapping table. The number of entries
in the interrupt remapping table is 2^(X+1), where X is the value programmed in this
field.