Specification Sheet

GFXVTBAR Registers
292 Datasheet, Volume 2 of 2
8.26 Invalidation Event Upper Address Register
(IEUADDR)—Offset ACh
Register specifying the Invalidation Event interrupt message upper address.
Access Method
Default: 0h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MA
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
31:2
0h
RW_L
MA: When fault events are enabled, the contents of this register specify the DWORD-
aligned address (bits 31:2) for the interrupt request.
1:0
0h
RO
Reserved (RSVD): Reserved.
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + ACh
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MUA
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0h
RW_L
MUA: Hardware implementations supporting Queued Invalidations and Extended
Interrupt Mode are required to implement this register.
Hardware implementations not supporting Queued Invalidations or Extended Interrupt
Mode may treat this field as RsvdZ.