Specification Sheet

Datasheet, Volume 2 of 2 291
GFXVTBAR Registers
8.24 Invalidation Event Data Register (IEDATA)—
Offset A4h
Register specifying the Invalidation Event interrupt message data.
This register is treated as RsvdZ by implementations reporting Queued Invalidation
(QI) as not supported in the Extended Capability register.
Access Method
Default: 0h
8.25 Invalidation Event Address Register (IEADDR)—
Offset A8h
Register specifying the Invalidation Event Interrupt message address.
This register is treated as RsvdZ by implementations reporting Queued Invalidation
(QI) as not supported in the Extended Capability register.
Access Method
Default: 0h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + A4h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EIMD
IMD
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0h
RW_L
EIMD: This field is valid only for implementations supporting 32-bit interrupt data
fields. Hardware implementations supporting only 16-bit interrupt data treat this field
as Rsvd.
15:0
0h
RW_L
IMD: Data value in the interrupt request.
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + A8h