Specification Sheet

Datasheet, Volume 2 of 2 289
GFXVTBAR Registers
8.22 Invalidation Completion Status Register (ICS)—
Offset 9Ch
Register to report completion status of invalidation wait descriptor with Interrupt Flag
(IF) Set.
This register is treated as RsvdZ by implementations reporting Queued Invalidation
(QI) as not supported in the Extended Capability register.
Access Method
Default: 0h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 9Ch
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
IWC
Bit
Range
Default &
Access
Field Name (ID): Description
31:1
0h
RO
Reserved (RSVD): Reserved.
0
0h
RW1CS
IWC: Indicates completion of Invalidation Wait Descriptor with Interrupt Flag (IF) field
Set. Hardware implementations not supporting queued invalidations implement this
field as RsvdZ.