Specification Sheet

GFXVTBAR Registers
286 Datasheet, Volume 2 of 2
8.19 Invalidation Queue Head Register (IQH)—Offset
80h
Register indicating the invalidation queue head. This register is treated as RsvdZ by
implementations reporting Queued Invalidation (QI) as not supported in the Extended
Capability register.
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
63:39
0h
RO
Reserved (RSVD): Reserved.
38:20
0h
RW
PHML: This register specifies the last host physical address of the DMA-protected
high-memory region in system memory. Hardware ignores and does not implement
bits 63:HAW, where HAW is the host address width.
19:0
0h
RO
Reserved (RSVD): Reserved.
Type: MEM
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 80h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
QH
RSVD
Bit
Range
Default &
Access
Field Name (ID): Description
63:19
0h
RO
Reserved (RSVD): Reserved.
18:4
0h
ROV
QH: Specifies the offset (128-bit aligned) to the invalidation queue for the command
that will be fetched next by hardware.
Hardware resets this field to 0 whenever the queued invalidation is disabled (QIES
field Clear in the Global Status register).
3:0
0h
RO
Reserved (RSVD): Reserved.