Specification Sheet

Datasheet, Volume 2 of 2 285
GFXVTBAR Registers
8.18 Protected High-Memory Limit Register
(PHMLIMIT)—Offset 78h
Register to set up the limit address of DMA-protected high-memory region. This
register should be set up before enabling protected memory through PMEN_REG, and
should not be updated when protected memory regions are enabled.
This register is always treated as RO for implementations not supporting protected high
memory region (PHMR field reported as Clear in the Capability register).
The alignment of the protected high memory region limit depends on the number of
reserved bits (N:0) of this register. Software may determine the value of N by writing
all 1s to this register, and finding most significant zero bit position below host address
width (HAW) in the value read back from the register. Bits N:0 of the limit register is
decoded by hardware as all 1s.
The protected high-memory base & limit registers functions as follows.
• Programming the protected low-memory base and limit registers with the same
value in bits HAW:(N+1) specifies a protected low-memory region of size 2^(N+1)
bytes.
• Programming the protected high-memory limit register with a value less than the
protected high-memory base register disables the protected high-memory region.
Software should not modify this register when protected memory regions are enabled
(PRS field Set in PMEN_REG).
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
63:39
0h
RO
Reserved (RSVD): Reserved.
38:20
0h
RW
PHMB: This register specifies the base of protected (high) memory region in system
memory. Hardware ignores, and does not implement, bits 63:HAW, where HAW is the
host address width.
19:0
0h
RO
Reserved (RSVD): Reserved.
Type: MEM
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 78h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
PHML
RSVD