Specification Sheet

GFXVTBAR Registers
282 Datasheet, Volume 2 of 2
8.15 Protected Low-Memory Base Register
(PLMBASE)—Offset 68h
Register to set up the base address of DMA-protected low-memory region below 4GB.
This register should be set up before enabling protected memory through PMEN_REG,
and should not be updated when protected memory regions are enabled.
This register is always treated as RO for implementations not supporting protected low
memory region (PLMR field reported as Clear in the Capability register).
The alignment of the protected low memory region base depends on the number of
reserved bits (N:0) of this register. Software may determine N by writing all 1s to this
register, and finding the most significant zero bit position with 0 in the value read back
from the register. Bits N:0 of this register is decoded by hardware as all 0s.
Software should setup the protected low memory region below 4GB.
Software should not modify this register when protected memory regions are enabled
(PRS field Set in PMEN_REG).
Access Method
Bit
Range
Default &
Access
Field Name (ID): Description
31
0h
RW
EPM: This field controls DMA accesses to the protected low-memory and protected
high-memory regions.
0: Protected memory regions are disabled.
1: Protected memory regions are enabled. DMA requests accessing protected memory
regions are handled as follows:
• When DMA remapping is not enabled, all DMA requests accessing protected
memory regions are blocked.
• When DMA remapping is enabled:
— DMA requests processed as pass-through (Translation Type value of 10b in
Context-Entry) and accessing the protected memory regions are blocked.
— DMA requests with translated address (AT=10b) and accessing the
protected memory regions are blocked.
— DMA requests that are subject to address remapping, and accessing the
protected memory regions may or may not be blocked by hardware. For
such requests, software should not depend on hardware protection of the
protected memory regions, and instead program the DMA-remapping page-
tables to not allow DMA to protected memory regions.
Remapping hardware access to the remapping structures are not subject to protected
memory region checks.
DMA requests blocked due to protected memory region violation are not recorded or
reported as remapping faults.
Hardware reports the status of the protected memory enable/disable operation
through the PRS field in this register. Hardware implementations supporting DMA
draining should drain any in-flight translated DMA requests queued within the Root-
Complex before indicating the protected memory region as enabled through the PRS
field.
30:1
0h
RO
Reserved (RSVD): Reserved.
0
0h
ROV
PRS: This field indicates the status of protected memory region(s):
0: Protected memory region(s) disabled.
1: Protected memory region(s) enabled.
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 68h