Specification Sheet

GFXVTBAR Registers
280 Datasheet, Volume 2 of 2
8.12 Fault Event Upper Address Register (FEUADDR)—
Offset 44h
Register specifying the interrupt message upper address.
Access Method
Default: 0h
8.13 Advanced Fault Log Register (AFLOG)—Offset 58h
Register to specify the base address of the memory-resident fault-log region. This
register is treated as RsvdZ for implementations not supporting advanced translation
fault logging (AFL field reported as 0 in the Capability register).
Access Method
Default: 0h
Bit
Range
Default &
Access
Field Name (ID): Description
31:2
0h
RW
MA: When fault events are enabled, the contents of this register specify the DWORD-
aligned address (bits 31:2) for the interrupt request.
1:0
0h
RO
Reserved (RSVD): Reserved.
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 44h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MUA
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0h
RW
MUA: Hardware implementations supporting Extended Interrupt Mode are required to
implement this register.
Hardware implementations not supporting Extended Interrupt Mode may treat this
field as RsvdZ.
Type: MEM
(Size: 64 bits)
Offset: [B:0, D:0, F:0] + 58h