Specification Sheet
Datasheet, Volume 2 of 2 277
GFXVTBAR Registers
8.9 Fault Event Control Register (FECTL)—Offset 38h
Register specifying the fault event interrupt message control bits.
Access Method
Default: 80000000h
2
0h
RO
AFO: Hardware sets this field to indicate advanced fault log overflow condition. At this
time, a fault event is generated based on the programming of the Fault Event Control
register.
Software writing 1 to this field clears it.
Hardware implementations not supporting advanced fault logging implement this bit
as RsvdZ.
1
0h
ROSV
PPF: This field indicates if there are one or more pending faults logged in the fault
recording registers. Hardware computes this field as the logical OR of Fault (F) fields
across all the fault recording registers of this remapping hardware unit.
0: No pending faults in any of the fault recording registers
1: One or more fault recording registers has pending faults. The FRI field is updated by
hardware whenever the PPF field is set by hardware. Also, depending on the
programming of Fault Event Control register, a fault event is generated when hardware
sets this field.
0
0h
RW1CS
PFO: Hardware sets this field to indicate overflow of fault recording registers.
Software writing 1 clears this field. When this field is Set, hardware does not record
any new faults until software clears this field.
Bit
Range
Default &
Access
Field Name (ID): Description
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 38h
3
1
2
8
2
4
2
0
1
6
1
2
8
4
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IM
IP
RSVD