Specification Sheet

GFXVTBAR Registers
276 Datasheet, Volume 2 of 2
8.8 Fault Status Register (FSTS)—Offset 34h
Register indicating the various error status.
Access Method
Default: 0h
Type: MEM
(Size: 32 bits)
Offset: [B:0, D:0, F:0] + 34h
3
1
2
8
2
4
2
0
1
6
1
2
8 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RSVD
FRI
PRO
ITE
ICE
IQE
APF
AFO
PPF
PFO
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0h
RO
Reserved (RSVD): Reserved.
15:8
0h
RO
FRI: This field is valid only when the PPF field is Set.
The FRI field indicates the index (from base) of the fault recording register to which
the first pending fault was recorded when the PPF field was Set by hardware.
The value read from this field is undefined when the PPF field is clear.
7
0h
RW1CS
PRO: Hardware detected a Page Request Overflow error. Hardware implementations
not supporting the Page Request Queue implement this bit as RsvdZ.
6
0h
RO
ITE: Hardware detected a Device-IOTLB invalidation completion time-out. At this time,
a fault event may be generated based on the programming of the Fault Event Control
register.
Hardware implementations not supporting device Device-IOTLBs implement this bit as
RsvdZ.
5
0h
RO
ICE: Hardware received an unexpected or invalid Device-IOTLB invalidation
completion. This could be due to either an invalid ITag or invalid source-id in an
invalidation completion response. At this time, a fault event may be generated based
on the programming of the Fault Event Control register.
Hardware implementations not supporting Device-IOTLBs implement this bit as RsvdZ.
4
0h
RW1CS
IQE: Hardware detected an error associated with the invalidation queue. This could be
due to either a hardware error while fetching a descriptor from the invalidation queue,
or hardware detecting an erroneous or invalid descriptor in the invalidation queue. At
this time, a fault event may be generated based on the programming of the Fault
Event Control register.
Hardware implementations not supporting queued invalidations implement this bit as
RsvdZ.
3
0h
RO
APF: When this field is Clear, hardware sets this field when the first fault record (at
index 0) is written to a fault log. At this time, a fault event is generated based on the
programming of the Fault Event Control register.
Software writing 1 to this field clears it. Hardware implementations not supporting
advanced fault logging implement this bit as RsvdZ.