Specification Sheet

Datasheet, Volume 2 of 2 35
Processor Configuration Register Definitions and Address Ranges
The PAM registers are mapped in Device 0 configuration space.
• ISA Expansion Area (C_0000h – D_FFFFh)
• Extended System BIOS Area (E_0000h – E_FFFFh)
• System BIOS Area (F_0000h – F_FFFFh)
The processor decodes the Core request, then routes to the appropriate destination
(DRAM or DMI).
Snooped accesses from PCI Express or DMI to this region are snooped on processor
Caches.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
Graphics translated requests to this region are not allowed. If such a mapping error
occurs, the request will be routed to C_0000h. Writes will have the byte enables de-
asserted.
Figure 2-4. PAM Region Space