Specification Sheet

GFXVTBAR Registers
268 Datasheet, Volume 2 of 2
34
1h
ROV
EAFS:
0: Hardware does not support the extended-accessed (EA) bit in first-level paging-
structure entries.
1: Hardware supports the extendedaccessed (EA) bit in first-level paging-structure
entries. This field is valid only when PASID field is reported as Set.
33
1h
ROV
NWFS:
0: Hardware ignores the "No Write" (NW) flag in Device-TLB translation requests, and
behaves as if NW is always 0.
1: Hardware supports the "No Write" (NW) flag in Device-TLB translation requests.
This field is valid only when Device-TLB support (DT) field is reported as Set.
32
0h
RO
POT:
0: Hardware does not support PASID-only Translation Type in extended-context-
entries
1: Hardware supports PASID-only Translation Type in extended-context-entries
31
0h
RO
SRS:
0: H/W does not support requests-with-PASID seeking supervisor privilege
1: H/W supports requests-with-PASID seeking supervisor privilege
30
0h
RO
ERS: 0: H/W does not support requests seeking execute permission
1: H/W supports requests seeking execute permission
29
1h
ROV
PRS:
0: Hardware does not support Page Requests
1: Hardware supports Page Requests
28
0h
RO
Reserved (RSVD): Reserved.
27
1h
ROV
DIS:
0: Hardware does not support deferred invalidations of IOTLB and Device-TLB.
1: Hardware supports deferred invalidations of IOTLB and Device-TLB.
26
1h
ROV
NEST:
0: Hardware does not support nested translations.
1: Hardware supports nested translations.
25
1h
ROV
MTS:
0: Hardware does not support Memory Type
1: Hardware supports Memory Type
24
1h
ROV
ECS:
0: Hardware does not support extended-root-entries and Extended Context-Entries
1: Hardware supports extended-root-entries and Extended Context-Entries
23:20
Fh
RO
MHMV: The value in this field indicates the maximum supported value for the Handle
Mask (HM) field in the interrupt entry cache invalidation descriptor (iec_inv_dsc).
This field is valid only when the IR field in Extended Capability register is reported as
Set.
19:18
0h
RO
Reserved (RSVD): Reserved.
17:8
50h
RO
IRO: This field specifies the offset to the IOTLB registers relative to the register base
address of this remapping hardware unit.
If the register base address is X, and the value reported in this field is Y, the address
for the first IOTLB invalidation register is calculated as X+(16*Y).
7
0h
RO
SC:
0: Hardware does not support 1-setting of the SNP field in the page-table entries.
1: Hardware supports the 1-setting of the SNP field in the page-table entries.
6
1h
ROV
PT:
0: Hardware does not support pass-through translation type in context entries.
1: Hardware supports pass-through translation type in context entries.
5
0h
RO
Reserved (RSVD): Reserved.
Bit
Range
Default &
Access
Field Name (ID): Description